1. Field of the Invention
The present invention relates to an NOR type nonvolatile semiconductor memory device for storing multi-valued data, for example, and particularly to a reference current generating circuit applied to a sense amplifier of the semiconductor memory device.
2. Description of the Related Art
There has been a variety of nonvolatile semiconductor storage devices (hereinafter, referred to as a memory) which are composed of EEPROM cells and electrically erased in batch, for example. NOR type flash memory readout and verify operations, for example, are executed by comparing currents that flow to a selected memory cell and a reference memory cell by means of a sense amplifier (for example, Jpn. Pat. Appln. KOKAI Publication No. 2004-103211, B. Pathak et al., A 1.8 V 64 Mb 100 MHz Flexible Reed While Write Flash Memory, 2001, IEEE International Solid-State Circuits Conference). This system is called a current comparison type sense system.
As the current comparison sense system, there are known two types of an Iref direct coupling system of directly supplying a reference current Iref to an input end of a sense amplifier and an Iref mirror system of supplying a reference Iref to an input end of a sense amplifier via a current mirror circuit.
The Iref direct coupling system uses a plurality of reference memory cells. Threshold voltages of reference memory cells each are not uniform, and have a dispersion. Thus, in order to reduce the dispersion of the threshold voltages of the reference memory cells, a long adjustment time is required. In contrast, the Iref mirror system has a merit that an adjustment time is reduced because only one reference memory cell is used.
On the other hand, with respect to a current margin for reading out data from a memory cell, the Iref mirror system is more excellent as compared with the Iref direct coupling system in both of a case of reading out data “0”from a memory for storing a two-valued state and a case of reading out data “1”. That is, voltage/current characteristics of memory cells in the Iref direct coupling system are substantially parallel to a gradient of voltage/current characteristics of a reference memory cell. Thus, in an effect on the sense current margin relevant to each of the memory cells which does not supply a current, the memory cells having stored data “0” and each of the memory cells which supplies a current, the memory cells having stored data “1” due to a threshold value fluctuation of a memory cell due to a temperature, the sense current margin on the memory cell side having stored data “0” is reduced. In contrast, in the case of the Iref mirror system, the voltage/current characteristics of a reference memory cell are specified in accordance with a mirror ratio of a current mirror circuit, and a different gradient with respect to a gradient of the voltage/current characteristics of the memory cell can be set. That is, the effect on the sense current margin relevant to the above-described fluctuation can be distributed to each of the memory cells having stored data “0” and data “1”.
In the meantime, recently, there has been developed a multi-value memory for storing a multi-valued state of 2 bits or more in one memory cell. In the case of the multi-value memory, more reference currents are required as compared with a two-value memory, and moreover, it is necessary to generate a plurality of reference currents with high accuracy. For example, when four-valued data are to be stored, it is necessary to generate three reference currents. In the case where a number of reference currents are thus generated, it becomes difficult to allocate a current margin relevant to the dispersion in a conventional Iref mirror system. Thus, there is proposed use of the Iref direct coupling system. However, in the case of the Iref direct coupling system, there is a need for reference memory cells whose number is equal to that of the reference currents. Thus, there is a problem that a long time is required for adjusting the reference memory cells.
Therefore, there is demand for a nonvolatile semiconductor memory device having a reference current generating circuit which is capable of reducing a time for adjusting a threshold voltage of a reference memory cell and which is capable of allocating a sufficient current margin.